Field of the Invention:
The invention lies in the semiconductor manufacturing and semiconductor technology fields. More specifically, the present invention relates to a method for fabricating a semiconductor structure and to a correspondingly fabricated semiconductor structure, and also to an installation for fabricating the structure and for carrying out the method.
In the context of DRAMs it is generally known to fabricate a contact on one side between a DRAM cell transistor and the storage electrode of a trench capacitor. The contact between the capacitor electrode and the source/drain region of the cell transistor is also known as a buried strap. The production of the buried strap causes particular problems in the case of a vertical transistor, especially if the corresponding memory cells cover a minimal chip area. This minimal chip area results if the cell area in units of the minimum feature size F that can be produced by lithography is selected to be minimal in accordance with the cell type. This results in high aspect ratios ( greater than 1:5) in the vertical transistor, and these ratios are additionally increased as F decreases, since the transistor length or the depth of the buried strap cannot readily be reduced.
In the case of planar transistors, the buried strap is structured by means of lithography in accordance with the prior art. In the case of the high aspect ratios of the vertical transistors which have been mentioned or similar deep trench semiconductor structures, this cannot be carried out. Inclined implantation for doping on one side also causes problems, because with the high aspect ratios that are present, there are problems with the scatter of the doping ions and their diffusion during activation.
Ronald A. Powell and Stephen Rossnagel describe a so-called long-throw PVD process in xe2x80x9cThin Filmsxe2x80x9d: PVD (Physical Vapor Deposition) for Microelectronics: Sputter Deposition applied to Semiconductor Manufacturing, Academic Press, San Diego, Calif., USA 1999, p. 191-195 as a process used in microelectronics for the deposition of diffusion barriers, such as Ti or TiN. It is customary to select a distance of approximately 30 cm between the magnetron cathode and the wafer surface.
The collimated PVD process is another known process used in microelectronics for deposition of diffusion barriers, such as Ti or TiN (Powell/Rossnagel p. 195-212). In the case of collimated PVD, atoms are bundled onto the wafer surface by the collimator, which acts as a direction filter and is formed from tubular elements arranged in an array. In theory, aspect ratios of from 0.5 to 4 are known in the literature for the collimator.
Furthermore, the I-PVD (ionized magnetron sputter deposition) process is known for the deposition of diffusion barriers, such as Ti and TiN and Ta and TaN (Powell/Rossnagel, p. 241-249). Unlike the above PVD processes, 80% of the deposited particles are ionized. They are directionally deposited on the wafer surface by action of a voltage. In that process, it is customary for the bias voltage to be applied directly to the wafer.
It is accordingly an object of the invention to provide a method and an installation for the production of buried straps on one side, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables the production of the buried straps in deep trench structures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a semiconductor structure, which comprises:
providing a semiconductor structure with a recess having a base, and a buried strap contact (e.g., forming a contact between a capacitor electrode and a source/drain region of a transistor in the semiconductor structure);
depositing masking material in the recess with PVD process deposition inclined at a tilting angle, to thereby form a masking wedge on the buried strap on one side in the base of the recess; and
subsequently anisotropically etching, using the masking wedge as a mask, and etching selectively with respect to the masking wedge, for removing the buried strap on one side in the base of the recess.
In other words, a mask which is produced in self-aligned fashion on one side at the bottom of the trench is used for the inventive structuring of the buried strap. According to the invention, methods which are based on targeted deposition of a suitable material are used to produce the mask. The position of the mask on one side in the trench is produced by the tilting of the wafer which is to be processed by the tilting angle xcex1 with respect to the main direction of deposition. This advantageously makes use of the shadow formation in the trench structure through the targeted deposition. The lateral dimensions of the mask which is produced may be significantly smaller than the minimum feature size F which can be produced by lithography, e.g. F/2. The mask can in this case be produced without the use of an expensive lithography step. Moreover, the mask which is produced is free of alignment errors such as those which occur in lithography, since it is produced in self-aligned fashion with respect to the trench structure. According to the invention, it is possible to use modified deposition processes which have in theory long been known in silicon technology, such as modified physical vapor deposition (PVD) and ionized physical vapor deposition (I-PVD). An essential factor of each of the installations according to the invention is that the angle spread xcex4, i.e. the deviation from the main direction, of the deposited particles is less than xc2x15xc2x0, in particular less than xc2x12xc2x0, and that the wafer is arranged tiltable in the installation.
The method is advantageously carried out using an I-PVD installation, since a process carried out with an installation of this type in particular has a higher yield than collimated PVD or long-throw PVD. According to a preferred embodiment, a grid electrode is arranged between a magnetron plasma and the surface of the wafer, a grid voltage being applied between the grid electrode and a wafer bench. This measure means that even when the wafer or wafer bench is tilted out of the horizontal, the angle spread of the ions which are being deposited as they move from the grid electrode onto the wafer can be limited to the required value; the inclination of the wafer relative to the grid electrode has no adverse effects. A grid width of around 100 xcexcm represents a good compromise between sufficient directing action on the part of the electrode, on the one hand, and good transmission properties with regard to the ions, on the other hand.
In accordance with an added feature of the invention, a preferred tilting angle lies between 4xc2x0 and 8xc2x0 relative to a vertical extent of the recess.
Preferably, the masking material is amorphous silicon (a-Si). Further, a covering layer of a material that can be etched selectively with respect to the amorphous silicon may be deposited on the base of the recess, above the buried strap, prior to depositing the amorphous silicon. The covering layer preferably comprises SiO2.
In accordance with an additional feature of the invention, the masking material is alumina Al2O3.
With the above and other objects in view there is also provided, in accordance with the invention, a PVD installation for depositing a masking wedge on a wafer, comprising:
a device for holding a wafer formed with a recess and a buried strap contact at a base of the recess;
a device for depositing masking material in the recess at a tilting angle to form a masking wedge, the device for depositing the masking material having an angle spread of deposited particles of less than xc2x15xc2x0, preferably less than xc2x12xc2x0; and
wherein the wafer and a deposition direction are tiltable relative to one another.
Finally, there is also provided, in accordance with the invention, a wafer having recesses, in particular having a deep trench capacitor with a vertical transistor, with buried strap contacts. The buried strap contacts are fabricated using the method as summarized above, and the buried strap contacts are therefore in each case arranged on one and the same side of the recess on the wafer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and installation for fabricating buried straps on one side, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.